Methods for polishing surfaces of semiconductor wafers such as silicon wafers required to be highly flat are broadly classified into two types: a double-side polishing process for simultaneously polishing both sides of a semiconductor wafer and a single-side polishing process for polishing only one side thereof. Single-side polishing processes are used in a wide variety of applications from lapping using a relatively stiff polishing cloth to final polishing using a relatively soft polishing cloth.
Here, a typical single-side polishing process using a conventional single-side polishing apparatus 10 will be described with reference to FIG. 1. The polishing apparatus 10 has a polishing head 12 holding a semiconductor wafer 1 with a backing plate 11 therebetween, and a rotatable platen 14 to which a polishing cloth 13 is bonded. The polishing head 12 includes a rotation mechanism for rotating the polishing head 12, and a transfer mechanism for moving the polishing head 12 inside and outside the rotatable platen 14. In this single-side polishing apparatus 10, the polishing head 12 holds the semiconductor wafer 1 and at the same time presses a polishing target surface of the semiconductor wafer 1 (i.e., the surface opposite to the polishing head 12) against the polishing cloth 13 bonded to the top of the rotatable platen 14. Both the polishing head 12 and the rotatable platen 14 are rotated to allow relative movement of the polishing head 12 and the rotatable platen 14, thereby performing chemical mechanical polishing only on the polishing target surface of the semiconductor wafer 1 with a polishing agent 16 being supplied from a polishing agent supply means 15.
Single-side polishing provides somewhat high flatness but not a completely flat surface. In particular, poor flatness at the periphery of a semiconductor wafer after polishing, which is referred to as “surface sag” has been unavoidable to date. To address this problem, attempts have been made to obtain a semiconductor wafer with high flatness by preventing surface sag due to polishing.
For example, JP H09-174394 A (PTL 1) discloses a method of polishing a semiconductor wafer, in which a polishing time required to complete polishing is divided into at least two stages and an interruption is scheduled between the divided polishing stages, thereby performing multi-step polishing on a single semiconductor wafer. In this polishing method, multi-step polishing is performed with an interruption being scheduled between polishing steps to prevent poor flatness caused due to possibly long polishing time, thereby inhibiting surface sag of the polished surface.